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      3 <title>CodeMirror: VHDL mode</title>
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     22     <li><a class=active href="#">VHDL</a>
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     26 <article>
     27 <h2>VHDL mode</h2>
     28 
     29 <div><textarea id="code" name="code">
     30 LIBRARY ieee;
     31 USE ieee.std_logic_1164.ALL;
     32 USE ieee.numeric_std.ALL;
     33 
     34 ENTITY tb IS
     35 END tb;
     36 
     37 ARCHITECTURE behavior OF tb IS
     38    --Inputs
     39    signal a : unsigned(2 downto 0) := (others => '0');
     40    signal b : unsigned(2 downto 0) := (others => '0');
     41     --Outputs
     42    signal a_eq_b : std_logic;
     43    signal a_le_b : std_logic;
     44    signal a_gt_b : std_logic;
     45 
     46     signal i,j : integer;
     47 
     48 BEGIN
     49 
     50     -- Instantiate the Unit Under Test (UUT)
     51    uut: entity work.comparator PORT MAP (
     52           a => a,
     53           b => b,
     54           a_eq_b => a_eq_b,
     55           a_le_b => a_le_b,
     56           a_gt_b => a_gt_b
     57         );
     58 
     59    -- Stimulus process
     60    stim_proc: process
     61    begin
     62         for i in 0 to 8 loop
     63             for j in 0 to 8 loop
     64                 a <= to_unsigned(i,3); --integer to unsigned type conversion
     65                 b <= to_unsigned(j,3);
     66                 wait for 10 ns;
     67             end loop;
     68         end loop;
     69    end process;
     70 
     71 END;
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     84 <p>
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